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As the give-way vessel it is your duty to avoid a collision. Typically, this means you must alter speed or direction to cross behind the other vessel (the stand-on vessel). If you see a green light crossing from left-to-right, you are the stand-on vessel, and should maintain course and speed.
Give-way vessel: The vessel that is required to take early and substantial action to keep out of the way of other vessels by stopping, slowing down, or changing course. Avoid crossing in front of other vessels.
When crossing paths, it is the give-way vessels responsibility to slow down or change course. 23. When you are in a speed zone posted as “slow speed, minimum wake” your vessel should be completely settled in the water.
boat operators
A navigation rule can be overlooked if necessary to avoid immediate danger.
The Navigation Rules are much like the rules of the road on the highway. They establish a consistent way to navigate safely and avoid collisions when two boats are crossing paths, are on course to meet head-on, or when one boat wishes to overtake another.
Three main types of navigation are celestial, GPS, and map and compass.
72 COLREGS
The primary purpose of the Navigation Rules is to keep people safe.
In complying with the navigation rules, operators must consider all dangers of navigation; risk of collisions; and any special conditions, including the limitations of the boats involved. These considerations may make a departure from the navigation rules necessary to avoid immediate danger.
3. Which of the following must follow Navigation Rules for a powerboat? When a sailboat turns on its motor, and is using it to make way, it then essentially becomes a powerboat under the Navigation Rules.
In establishing a safe operating speed, the operator must take into account visibility; traffic density; ability to maneuver the vessel (stopping distance and turning ability); background light at night; proximity of navigational hazards; draft of the vessel; limitations of radar equipment; and the state of wind, sea.
To determine a ‘safe speed’ for your boat, take into account the following factors: The visibility conditions (fog, mist, rain, darkness) The wind, water conditions and currents. Traffic density, type of vessels in the area and their proximity.
In determining a safe speed the following factors shall be among those taken into account: (a) By all vessels: (i) the state of visibility; (ii) the traffic density including concentrations of fishing vessels or any other vessels; (iii)the manoeuvrability of the vessel with special reference to stopping distance and.
When approaching a narrow channel, stay to the starboard side and, using a prolonged blast, announce your approach to vessels that may be around the bend. When operating within a narrow channel, vessels must keep as near as is safe and practical to the outer limit of a narrow channel on their starboard side.
If you are operating a power-driven vessel and are heading upstream, all power-driven vessels coming toward you from the opposite direction (heading downstream) have the right-of-way and you must give way.
(a) A vessel proceeding along the course of a narrow channel or fairway shall keep as near to the outer limit of the channel or fairway which lies on her starboard side as is safe and practicable.
It is concluded that three main mechanisms coexist: (i) the local thinning of the film under the LOCOS isolation, (ii) a lower carrier lifetime near the channel edges and (iii) an increase of the source/body junction leakage near the edges which speeds up the removal of the carriers from the body.
Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells.
Hot electron effects can be reduced by reducing the doping in the source and drain regions, so that the junction fields are smaller. However lightly doped source and drain regions are incompatible with small geometry devices because of contact resistances and other similar problems.
Compared to a planar process in the same technology node, FinFET have reduced channel and gate leakage currents. The second gate can be used to control the threshold voltage of the device, thereby allowing fast switching on one side and reduced leakage currents when circuits are idle.
FinFET is suitable for future nanoscale memory circuits design due to its reduced short-channel effects (SCEs) and leakage current [6]. This technique provides increased operating speed by low-threshold MOSFET and reduced leakage by high-threshold voltage.
Several device structures have been proposed to alleviate the degrading effect of the drain electric field on device performance of sub-micron SOI MOSFET’s as discussed below. Reduction of short-channel effects in FD SOI MOSFETs requires the use of thin silicon films to eliminate the sub-surface leakage paths.
This structure is called the FinFET because its Si body resembles the back fin of a fish. In bulk-MOS (planner MOS), the channel is horizontal. While in FinFET channel, it is vertical. So for FinFET, the height of the channel (Fin) determines the width of the device.
The FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal-oxide-semiconductor) technology. FinFET is a type of non-planar transistor, or “3D” transistor. It is the basis for modern nanoelectronic semiconductor device fabrication.
The trigate FET and FINFET were introduced as welcome alternatives to the planar MOSFET. FINFET became more popular primarily due to its structural simplicity and easy fabrication. In this chapter, we attempt at the conceptual evolution of trigate FET/FINFET from the primeval planar MOSFET structure.
Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor at the University of California, Berkeley who were the first to coin the term as a result of the shape of the structure. FinFETs are 3d structures that rise above the substrate and resemble a fin.
Gate-all-around is the leading contender beyond finFETs, at least for now. Longer term, there are other options, such as III-V finFETs, complementary FETs (CFETs), TFETs and vertical nanowires.
Moore’s Law refers to Moore’s perception that the number of transistors on a microchip doubles every two years, though the cost of computers is halved. Moore’s Law states that we can expect the speed and capability of our computers to increase every couple of years, and we will pay less for them.
PODE = Poly Over Diffusion Edge. PDK = Process Design Kit. PPA = Power, Performance, Area. Acronyms.